1. Field of the Invention
Embodiments of the present invention generally relate to detecting defects in semiconductor products and, more particularly, to classifying and grouping systematic defects.
2. Description of the Related Art
Semiconductor devices, such as integrated circuits, are typically manufactured by replicating patterns onto a surface of a device substrate. The replication process typically involves lithographically transferring a pattern that is on a mask (or reticle) onto the device substrate using an illumination source, such as electron beam, x-ray, or optical source. In some cases, rather than use a mask, a beam is controlled in a raster or vector scan onto the resist, turning the scanned beam on and off in order to expose or not expose various portions of the resist.
A goal in lithography is to maintain uniformity of each instance of an identical structure imaged or “printed” onto the substrate. In some cases, there may be systematic defects in structures that arise from a variety of causes. These causes may include imperfections in components of the lithography tool, such as optical lenses, electrostatic, and/or electromagnetic lenses. Defects may also be caused by shifting lithography parameters, such as illumination focus and exposure. Further, because scanning lithography is typically used not only to write patterns to fabricate semiconductor devices, but also to fabricate masks used therein, such systematic defects may arise in both cases.
Some defects also arise due to design-process interactions (DPI defects). In other words, DPI defects arise due to the sensitivity of particular designs to process variations, such as variations in resist sensitivity at different positions on a substrate (e.g., caused by imperfections in a baking process), resist thickness, resist development and/or etching steps. Defects resulting from proximity effects, caused by influence of neighboring or nearby structures, may also increase with some process recipes due to sensitivity of certain patterned structures to changing process recipes.
As technology nodes advance, lithography systems and manufacturing processes are called upon to produce structures having smaller and smaller dimensions. Unless measures are taken to reduce variations in manufacturing processes the number of defects will typically increase in inverse proportion to feature size. Another approach, referred to as design for manufacturability (DFM), is to generate designs that are less sensitive to anticipated process variations, thereby reducing the number DPI defects and improving product yield.
Inspection tools are often utilized during mass production, where efforts are focused on random defects and process monitoring, in an effort to assure that the process does not drift. One example of such an inspection tool is the UVision Inspection system, available from Applied Materials of Santa Clara, Calif., which utilizes multi-beam deep ultra-violet (DUV) laser illumination and highly sensitive photo-detectors to generate high fidelity 3D images allowing a wide variety of defects to be detected. Such inspection tools typically generate defect maps identifying possibly tens of thousands to hundreds of thousands of defects at various locations in a semiconductor wafer.
Unfortunately, the sheer volume of these defects makes it challenging to extract meaningful data regarding DPI defects. The individual defects typically identify locations where a critical dimension (CD) has deviated beyond an acceptable tolerance (possibly leading to electrical shorts, voids, or breaks). As such, substantial and time consuming analysis and parsing of the individual defects would be required in order to identify design-process interaction and identify required changes in design or process. Further, many of the defects are repetitive due to the repetitive nature of the majority of device layouts. In other words, similar defect mechanisms will typically trigger multiple defects on various locations across the die. However, manually inspecting defect maps and design layout in an effort to correlate these repetitive defects into their unique defect mechanisms is time and cost prohibitive.
In some cases, simulations (e.g., optical proximity correction-OPC modeling) may be performed to identify failure-potential locations (“hot-spots”) across the die, for example, in an effort to focus defect inspection on a limited number of locations and, therefore, reduce the time and cost for meaningful analysis. Unfortunately, not all of these identified hot-spots actually result in defects. Conversely, not all of the actual defects are predicted by the modeling simulation.
Accordingly, there is a need for improved techniques for grouping and identifying systematic defects in semiconductor wafers, as well as masks used in lithographic writing of patterns.